1. Field of the Invention
The present invention relates to a polyphase filter and a receiver using thereof.
2. Description of the Related Art
With regard to digital audio broadcasting system, DAB (Digital Audio Broadcasting complies with Eureka 147 standard) system is adopted in Europe, and ISDB-T (Integrated Services Digital Broadcasting for Terrestrial) system is proposed in Japan.
ISDB-T system employs:
transmission band width of 432 kHz (for narrow-band ISDB-T system);
modulation system of OFDM (Orthogonal Frequency Division Multiplex); and
multiplexing system of MPEG2 (Moving Picture Experts Group 2); which enable simultaneous broadcasting of digital audio data and digital data in a plurality of channels. Broadcasting based on the narrow-band ISDB-T system is now planned to use the current VHF television broadcasting band.
One example of an ISDB-T receiver is typically composed as shown in FIG. 5. The figure shows a narrow-band ISDB-T receiver employing a super heterodyne configuration.
Broadcasting wave based on the narrow-band ISDB-T system is received by an antenna 11, the received signal is then fed to an antenna tuning circuit 12 based on the electronic tuning system, thereby a received signal SRX having a target frequency is extracted. The extracted signal SRX is then fed to mixer circuits 15I, 15Q via a variable gain amplifier 13 and an inter-stage tuning circuit 14 based on the electronic tuning system.
On the other hand, an oscillation signal having a predetermined frequency is generated by a PLL (Phase Locked Loop) 31, the oscillation signal from the PLL 31 is then fed to a frequency dividing circuit 32, where the oscillation signal is divided into two signals having a frequency higher, for example, by 500 kHz than a carrier frequency (center frequency) of the received signal SRX and differ by 90xc2x0 with each other in phase, the divided signals are then supplied to the mixer circuits 15I, 15Q as local oscillation signals.
Thus the received signal SRX is frequency-converted at the mixer circuits 15I, 15Q to generate two intermediate frequency signals SIFI and SIFQ (having a center frequency of 500 kHz) differ by 90xc2x0 with each other in phase, that is, an in-phase intermediate frequency signal SIFI and a quadrature intermediate frequency signal SIFQ orthogonal with each other.
In this process, a part of control voltage supplied from the PLL 31 to a variable capacity diode (not shown) of its VCO (Voltage Controlled Oscillator), is extracted, and the extracted control voltage is fed to the tuning circuit 12 as a tuning voltage, which allows tuning to the received signal SRX.
The intermediate frequency signals SIFI and SIFQ from the mixer circuits 15I, 15Q are then individually supplied to phase shifting circuits 17I, 17Q via the low pass filters 16I, 16Q, where the signals SIFI and SIFQ are phase-shifted by xcfx86 and xcfx86+90xc2x0, respectively. The phase-shifted signals are then supplied to an adder circuit 18, from which an intermediate frequency signal SIF having only a desired signal component is extracted while image signal components being canceled.
The intermediate frequency signal SIF is then supplied on a signal line comprising a bandpass filter 19 for filtering intermediate frequency component, a variable gain amplifier 21 for AGC (Automatic Gain Control) and a low pass filter 22 to a demodulation circuit 23, where the signal is subjected to demodulation processing corresponded to the modulation processing at the time of the ISDB-T transmission, and audio signals L, R of a desired program selected from a plurality of programs (channels) are extracted from such demodulation circuit 23.
Such receiver can be integrated into an one-chip integrated circuit (IC) except the tuning circuits 12, 14, an oscillation circuit of VCO in the PLL 31 and the demodulation circuit 23.
The phase shifting circuits 17I, 17Q and the adder circuit 18 now can be composed by a polyphase filter 17 as shown in FIG. 6.
In this configuration, a serial connection circuit consisting of a resistor R11 and a capacitor C11 is inserted between input terminals 17A and 17B; a serial connection circuit consisting of a resistor R21 and a capacitor C21 is inserted between input terminals 17B and 17C; a serial connection circuit consisting of a resistor R31 and a capacitor C31 is inserted between input terminals 17C and 17D; and a serial connection circuit consisting of a resistor R41 and a capacitor C41 is inserted between input terminals 17D and 17A.
A serial circuit consisting of a resistor R12 and a capacitor C12 is inserted between the output side of the resistor R11 (connection point of the resistor R11 and the capacitor C11) and the output side of the resistor R21 (connection point of the resistor R21 and the capacitor C21); a serial circuit consisting of a resistor R22 and a capacitor C22 is inserted between the output sides of the resistor R21 and the output side of the resistor R31; a serial circuit consisting of a resistor R32 and a capacitor C32 is inserted between the output side of the resistor R31 and the output side of the resistor R41; and a serial circuit consisting of a resistor R42 and a capacitor C42 is inserted between the output side of the resistor R41 and the output side of the resistor R11.
Similarly, serial connection circuits individually consisting of resistors R13 to R43 and capacitors C13 to C43 are connected to the respective output sides of the resistors R12 to R42. The individual output sides of the resistors R13 and R23 are connected to an output terminal 17E, and the individual output sides of the resistors R33 and R43 are connected to an output terminal 17F.
The outputs from the low pass filters 16I and 16Q are balanced type, and the intermediate frequency signal SIFI output from the low pass filter 16I is supplied between the output terminals 17A and 17C, and the intermediate frequency signal SIFQ output from the low pass filter 16Q is supplied between the output terminals 17B and 17D. Thus an intermediate frequency signal having only a desired signal component is output in a balanced type between the output terminals 17E and 17F while image signal components being canceled.
Such polyphase filter 17 is advantageous in that it can be fabricated into an IC, and in that it is stable in the characteristic against non-uniformity in the fabrication of the IC devices and can ensure thorough elimination of the image signal component according to the foregoing method, since the resistors R11 to R43 and the capacitors C11 to C43 composing the polyphase filter 17 are in bridge connection.
In the polyphase filter 17, a frequency f17 receiving 90xc2x0 phase shifting is now expressed as
f17=1/(2xcfx80CR)
where, CR is a product of values for the resistors and the capacitors in the individual stages. The number of the stages of the polyphase filter 17 is determined based on the amount of attenuation required for suppressing the image signal components and specific band.
When fabricating the polyphase filter 17 into an IC, the capacitors C11 to C43 can be constituted by a metal-insulator-semiconductor (MIS) capacitor as shown in FIG. 7A. In this figure, on a p-type semiconductor substrate 71, formed are an n-type epitaxial layer 72, an n+-type buried region 73 and a p+-type isolation region 74.
An n+-type semiconductor layer 75 is formed in a superficial area of the epitaxial layer 72, and thereon an SiO2 layer 76 and an extra thin insulating layer 77 are formed. Further thereon an electrode 78 is formed so as to contact the semiconductor layer 75, and an electrode 79 is formed so as to be opposed to the n+-type semiconductor layer 75 while being interposed by the insulating layer 77. The electrodes 78, 79 are generally made of aluminum.
The electrode 78, the insulating layer 77 and the n+-type semiconductor layer 75 are thus combined to form a capacitor Cm as shown in FIG. 7B, where the electrodes 78 and 79 serves as outlet terminals of the capacitor Cm. The symbol xe2x80x9crxe2x80x9d represents resistance component of the n+-type semiconductor layer 75. In the polyphase filter 17 fabricated in an IC, the capacitors C11 to C43 can individually be materialized by such MIS-type capacitor Cm.
The MIS-type capacitor Cm is advantageous in that reducing the occupied area of the capacitors C11 to C43 in the polyphase filter 17 fabricated in an IC, since the capacitor of this type has a large capacitance per unit area.
In the MIS-type capacitor Cm, however, the semiconductor layer 75 is electrically connected to the buried region 73 via the epitaxial layer 72, and the buried layer 73 and the substrate 71 together form a p-n junction. This is equivalent to that, as shown in FIG. 7C, a p-n junction Ds contributed by the buried layer 73 and the substrate 71 is connected on the electrode 79 side of the capacitor Cm.
The p-n junction Ds is reversely biased when the MIS-type capacitor Cm operates, so that, as shown in FIG. 7D, the p-n junction Ds will act as a parasitic capacitor Cs. The parasitic capacitor Cs accounts for 5 to 10% of the main capacitor Cm, and the influence thereof on the polyphase filter 17 is not negligible.
FIG. 8 shows an equivalent circuit of the polyphase filter 17 in which the capacitors C11 to C43 are materialized as the MIS capacitor Cm, where the parasitic capacitor Cs also inclusive. The parasitic capacitors Cs appear on the output side of every stage. The parasitic capacitors Cs, and the resistors R11 to R43 in the previous stage thereof individually form low pass filters, which will lower the levels of the intermediate frequency signals SIFI and SIFQ passing through the polyphase filter 17.
It is thus necessary to compensate such lowering in the signal level, either by enhancing the drive ability of the output stage of the low pass filters 16I, 16Q in the former stage of the polyphase filter 17, or by raising the gain as well as reducing noise of the band pass filter 19 in the latter stage. Both methods, however, can merely compensate the signal loss in the polyphase filter 17, and cannot be an essential solution.
It is therefore an object of the present invention to solve the foregoing problem.
According to one aspect of the present invention, provided is a polyphase filter including a plurality of bridge circuits in a cascade connection, each bridge circuit being composed of four sets of serial connection circuit, and each serial connection circuit being composed of a resistor and a capacitor serially connected thereto, wherein the polyphase filter as a whole is fabricated into an integrated circuit; the capacitor is composed of a metal-insulator-semiconductor capacitor; and the metal-insulator-semiconductor capacitor is fabricated into the integrated circuit so that a parasitic capacitor accompanying said metal-insulator-semiconductor capacitor is connected to a connection point between the serial connection circuits.
According to another aspect of the present invention, provided is a polyphase filter including a plurality of bridge circuits, each bridge circuit being composed of four sets of serial connection circuit, and each serial connection circuit being composed of a resistor and a capacitor serially connected thereto, connection points between each adjacent ones of four serial connection circuits being provided as signal input terminals, connection points between the individual resistors and the individual capacitors in the individual serial connection circuits being provided as signal output terminals, a plurality of the bridge circuits being individually connected in a cascade manner via the signal input terminal and the signal output terminal, a first input signal being supplied to a first pair of the opposing signal input terminals of the bridge circuit in the first stage of a plurality of the bridge circuits in the cascade connection, a second input signal being supplied to a second pair of the opposing signal input terminals of the bridge circuit in the first stage, a first pair of the adjacent signal output terminals of the bridge circuits in the last stage of the bridge circuits in the cascade connection being connected with each other to provide a first signal output terminal, a second pair of the adjacent signal output terminals of the bridge circuits in the last stage being connected with each other to provide a second signal output terminal, so as to obtain output signals from the first and second signal output terminals; wherein the polyphase filter as a whole is fabricated into an integrated circuit; the capacitor is composed of a metal-insulator-semiconductor capacitor; and the metal-insulator-semiconductor capacitor is fabricated into the integrated circuit so that a parasitic capacitor accompanying said metal-insulator-semiconductor capacitor is connected to a connection point between the serial connection circuits composing the individual bridge circuits.
According to still another aspect of the present invention, provided is a receiver comprising:
a tuning circuit for extracting a signal to be received having a target frequency from received signals;
a first mixer circuit and a second mixer circuit to which the signal to be received extracted by the tuning circuit is supplied;
a circuit for supplying to the first and the second mixer circuits a first local oscillation signal and a second local oscillation signal being differed by 90xc2x0 with each other in phase;
a polyphase filter to which a first intermediate frequency signal and a second intermediate frequency signal being differed by 90xc2x0 with each other in phase output from the first and the second mixer circuits are supplied; and a demodulation circuit to which an output signal from the polyphase filter is supplied; wherein, the polyphase filter is as a whole fabricated into an integrated circuit; and includes a plurality of bridge circuits in a cascade connection, each bridge circuit being composed of four sets of serial connection circuit, and each serial connection circuit being composed of a resistor and a capacitor serially connected thereto; the capacitor being composed of a metal-insulator-semiconductor capacitor; and the metal-insulator-semiconductor capacitor being fabricated into the integrated circuit so that a parasitic capacitor accompanying said metal-insulator-semiconductor capacitor is connected to a connection point between the serial connection circuits composing the individual bridge circuits.
According to the present invention, effects of the parasitic capacitor which is likely to be produced when the capacitor of the polyphase filter is materialized by the MIS capacitor can be reduced, and thus a desired phase shifting characteristic can be obtained without correcting the transit characteristic of the polyphase filter.
It is also unnecessary to raise the gain in the former stage of the polyphase filter, nor to raise the gain and to reduce noise in the latter stage. This allows the receiver using such polyphase filter to improve its image signal characteristic.